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DDC-I announces DO-178C safety-critical multi-core RTOS for NXP i.MX 95 applications processor

30/04/2026

Press releaseIssued by DDC-I, Inc..

DDC-I, a leading supplier of software for mission- and safety-critical applications, today announced availability of the Deos DO-178C multi-core real-time operating system (RTOS) for the NXP Semiconductors i.MX 95 applications processor with verification evidence to Design Assurance Level (DAL) A. The NXP i.MX 95 applications processor with the Deos RTOS extends and strengthens the i.MX 95 SoC’s applicability in safety and mission critical aerospace markets. Use cases include a broad range of embedded control, display, and intelligent sensors.

“Many of the same attributes that make the i.MX 95 SoC well-suited for an eCockpit platform for automotive applications and machine vision platform for industrial control and automation applications make it equally attractive for a multitude of aerospace applications requiring adaptive control, high-performance graphics and/or synthetic vision,” said Jeff Steinheider, Vice President of Marketing, Industrial and Network Segments at NXP. “We are pleased to be working with DDC-I to offer our joint avionics customers a world-class multi-core safety-critical RTOS platform for our i.MX 95 Application Processors.”

“NXP’s i.MX 95 provides an optimized blend of processing capabilities, versatile I/O, Ethernet and TSN networking, 3D graphics, video processing, and security features within a highly integrated lower wattage SoC device. This makes it well-suited for a number of avionics applications and, as a result, DDC-I has already seen Deos customers commit to this processor for display and control applications,” said Gary Gilliland, Vice President of Marketing at DDC-I. “Deos, with features such as cache partitioning and safe scheduling, enable developers to run high throughput and processor intensive applications deterministically, reliably, securely, and safely.”

The i.MX 95 family provides up to six Arm Cortex-A55 cores together with an independent safety domain consisting of high-performance Arm Cortex-M7 and Arm Cortex-M33 CPUs. It also combines an Arm Mali-powered 3D, multi-display graphics, an accelerator for machine learning, and an image signal processor (ISP). The integrated secure enclave simplifies implementation of security critical functions like secure boot, cryptography, trust provisioning, and run-time attestation.

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