White Electronic Designs Corporation (NASDAQ:WEDC) is pleased to introduce its 4Gb (512MB) DDR SDRAM PBGA Multi-Chip Package (MCP). The SDRAM is organized as 64M x 72, packaged in a 25 x 32mm, 800mm2 , 219 plastic ball grid array (PBGA). This package is suitable for high-reliability applications and is available at data rates of 200, 250, 266 and 333 Mbs in commercial, industrial and military temperature ranges.

Benefits include a 66% space savings versus a comparable density using thin small-outline packages (TSOPs), 55% I/O reduction versus TSOP, reduced trace lengths for lower parasitic capacitance and reduced part count. It delivers high density for increased performance.

WEDC's new DDR SDRAM MCP features internal pipelined double-data-rate (DDR) architecture enabling two data accesses per clock cycle. The SDRAM provides programmable Read or Write burst lengths of 2, 4 or 8, four internal banks allow concurrent operation and it features bi-directional data strobe (DQS, DQS#) per byte for transmitting and receiving data.